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Macros</h2></td></tr>
<tr class="memitem:affb7c95abd8cad50d7efa83f94ea3344"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;(Xil_In32(((BaseAddress) + (RegOffset))))</td></tr>
<tr class="separator:affb7c95abd8cad50d7efa83f94ea3344"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac6e57b26c1f5674deb7c571dc319bf9e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;Xil_Out32(((BaseAddress) + (RegOffset)), (Data))</td></tr>
<tr class="separator:ac6e57b26c1f5674deb7c571dc319bf9e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a29995f5e78072a8756081fed9ccb36bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a29995f5e78072a8756081fed9ccb36bd">XTrafGen_ReadParamRam</a>(BaseAddress,  Offset)&#160;&#160;&#160;(Xil_In32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga3252ba966b4231b39738858474879b33">XTG_PARAM_RAM_OFFSET</a> + (Offset))))</td></tr>
<tr class="separator:a29995f5e78072a8756081fed9ccb36bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:affbc767805f25351f801dc04114d513f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#affbc767805f25351f801dc04114d513f">XTrafGen_WriteParamRam</a>(BaseAddress,  Offset,  Data)&#160;&#160;&#160;Xil_Out32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga3252ba966b4231b39738858474879b33">XTG_PARAM_RAM_OFFSET</a> + (Offset)), (Data))</td></tr>
<tr class="separator:affbc767805f25351f801dc04114d513f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a04a570c3b4cc407d745237050374013c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a04a570c3b4cc407d745237050374013c">XTrafGen_ReadCmdRam</a>(BaseAddress,  Offset)&#160;&#160;&#160;(Xil_In32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga1b4f5daeb95b5827db0760c1c0dc13e5">XTG_COMMAND_RAM_OFFSET</a> + (Offset))))</td></tr>
<tr class="separator:a04a570c3b4cc407d745237050374013c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab9c29e9e8361e7dc553c689e7cfd8ee1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ab9c29e9e8361e7dc553c689e7cfd8ee1">XTrafGen_ReadCmdRam_Msb</a>(BaseAddress,  Offset)&#160;&#160;&#160;(Xil_In32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga6fd650735d7eb15cc3cd76679f8b7894">XTG_COMMAND_RAM_MSB_OFFSET</a> + (Offset))))</td></tr>
<tr class="separator:ab9c29e9e8361e7dc553c689e7cfd8ee1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a25bf6ea33be9bb74e718dc810c6760f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a25bf6ea33be9bb74e718dc810c6760f5">XTrafGen_WriteCmdRam</a>(BaseAddress,  Offset,  Data)&#160;&#160;&#160;Xil_Out32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga1b4f5daeb95b5827db0760c1c0dc13e5">XTG_COMMAND_RAM_OFFSET</a> + (Offset)), (Data))</td></tr>
<tr class="separator:a25bf6ea33be9bb74e718dc810c6760f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afebb93dc8864de6d9466a5fd6355c117"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#afebb93dc8864de6d9466a5fd6355c117">XTrafGen_WriteCmdRam_Msb</a>(BaseAddress,  Offset,  Data)&#160;&#160;&#160;Xil_Out32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga6fd650735d7eb15cc3cd76679f8b7894">XTG_COMMAND_RAM_MSB_OFFSET</a> + (Offset)), (Data))</td></tr>
<tr class="separator:afebb93dc8864de6d9466a5fd6355c117"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a60ceec5d839e8a8f1cdda74c93c425b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a60ceec5d839e8a8f1cdda74c93c425b8">XTrafGen_ReadMasterRam</a>(BaseAddress,  Offset)&#160;&#160;&#160;(Xil_In32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga5f8872e23f0ea33fda1193c114fa9224">XTG_MASTER_RAM_OFFSET</a> + (Offset))))</td></tr>
<tr class="separator:a60ceec5d839e8a8f1cdda74c93c425b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8fe8b5ce12fefb6bba6acee1b89cb2a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a8fe8b5ce12fefb6bba6acee1b89cb2a7">XTrafGen_WriteMasterRam</a>(BaseAddress,  Offset,  Data)&#160;&#160;&#160;Xil_Out32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga5f8872e23f0ea33fda1193c114fa9224">XTG_MASTER_RAM_OFFSET</a> + (Offset)), (Data))</td></tr>
<tr class="separator:a8fe8b5ce12fefb6bba6acee1b89cb2a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Device registers</div></td></tr>
<tr class="memitem:gafee2ca23e3fc2ed4964740ba69dde023"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a>&#160;&#160;&#160;0x60</td></tr>
<tr class="separator:gafee2ca23e3fc2ed4964740ba69dde023"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Internal RAM Offsets</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Master Control Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_MCNTL_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Slave Control Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_SCNTL_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Error bitmasks</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are shared with the XTG_ERR_STS_OFFSET and XTG_ERR_EN_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Master Error Interrupt Enable Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_MSTERR_INTR_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Config Status Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_CFG_STS_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Streaming Control Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_STR_CFG_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Streaming Config Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_STR_CFG_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Streaming Transfer Length Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_STR_TL_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Static Control Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_STATIC_CNTL_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Static Length Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_STATIC_LEN_OFFSET register. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Axi Traffic Generator Command Entry field mask/shifts</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Axi Traffic Generator Parameter Entry field mask/shifts</div></td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a575795d7d5b2348195e02fd8cccabe39"></a>
<div class="memitem">
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          <td class="memname">#define XTG_ADDR_MASK&#160;&#160;&#160;0xFFFFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_addr line. </p>

</div>
</div>
<a class="anchor" id="a4fec29a2aedb84ed9410fe5298245d24"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XTG_ADDR_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_addr line. </p>

</div>
</div>
<a class="anchor" id="ae149dfc387f997a33cbe70d57362fc0f"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XTG_BURST_MASK&#160;&#160;&#160;0x3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_burst line. </p>

</div>
</div>
<a class="anchor" id="a70414e4d0c831df19899fe7c050a7a03"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XTG_BURST_SHIFT&#160;&#160;&#160;10</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_burst line. </p>

</div>
</div>
<a class="anchor" id="a3b4631d92345fd27ee3e40d827a184f3"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XTG_CACHE_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_cache line. </p>

</div>
</div>
<a class="anchor" id="a6496641578aa8a7a22dd3c6147221175"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_CACHE_SHIFT&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_cache line. </p>

</div>
</div>
<a class="anchor" id="a73aac9edd6e776525f4e44865ed7e481"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XTG_CFG_STS_MBASIC_MASK&#160;&#160;&#160;0x00800000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Basic Mode. </p>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a1816012cab8ec1b93b06d20dde1e0128"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XTG_CFG_STS_MFULL_MASK&#160;&#160;&#160;0x01000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Full Mode. </p>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a7387f793b21568825291b8ae05e9a8dc"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XTG_CFG_STS_MWIDTH_MASK&#160;&#160;&#160;0x70000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Master Width Mask. </p>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a43010263c928054845a6e4da818c5cb6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define XTG_CFG_STS_MWIDTH_SHIFT&#160;&#160;&#160;28</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Master Width Shift. </p>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a641638626484a52b81fbbf8f30bd45dc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define XTG_CFG_STS_SWIDTH_MASK&#160;&#160;&#160;0x0E000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Slave Width Mask. </p>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ab8521be4a5dc1628cb3a3afe87298843"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_CFG_STS_SWIDTH_SHIFT&#160;&#160;&#160;25</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Slave Width Shift. </p>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ad893dd4b8011e14e68b21afa20c019c8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_EXPECTED_RESP_MASK&#160;&#160;&#160;0x7</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Expected response. </p>

</div>
</div>
<a class="anchor" id="abc9721f5268f2b05074b669d5603b1e7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_EXPECTED_RESP_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Expected response. </p>

</div>
</div>
<a class="anchor" id="a5a7178fbdfb4b46aaa7bd0fc308ec636"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XTG_ID_MASK&#160;&#160;&#160;0x3F</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_id line. </p>

</div>
</div>
<a class="anchor" id="abf8893d48139c874e7628a7d32d1861b"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XTG_ID_SHIFT&#160;&#160;&#160;15</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_id line. </p>

</div>
</div>
<a class="anchor" id="a9267c6248c021a02be574f803f11c677"></a>
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          <td class="memname">#define XTG_LAST_ADDR_MASK&#160;&#160;&#160;0x7</td>
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<p>Last address. </p>

</div>
</div>
<a class="anchor" id="ab2e214bbd75cfa106a9cf34a075ca7c3"></a>
<div class="memitem">
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          <td class="memname">#define XTG_LAST_ADDR_SHIFT&#160;&#160;&#160;28</td>
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<p>Last address. </p>

</div>
</div>
<a class="anchor" id="a74fdcca6bba8dfbfd0ed288f9132bab0"></a>
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          <td class="memname">#define XTG_LEN_MASK&#160;&#160;&#160;0xFF</td>
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<p>Driven to a*_len line. </p>

</div>
</div>
<a class="anchor" id="ae25779b53195ced1e45d64bc53344c28"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XTG_LEN_SHIFT&#160;&#160;&#160;0</td>
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<p>Driven to a*_len line. </p>

</div>
</div>
<a class="anchor" id="a6575f2dffb01e56c6b38eda8190664b8"></a>
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          <td class="memname">#define XTG_LOCK_MASK&#160;&#160;&#160;0x1</td>
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<p>Driven to a*_lock line. </p>

</div>
</div>
<a class="anchor" id="a819696f324a87fbdf9dbce5c6aafcdaf"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XTG_LOCK_SHIFT&#160;&#160;&#160;8</td>
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<p>Driven to a*_lock line. </p>

</div>
</div>
<a class="anchor" id="a7f69f7e850cdf6eaeacb76be85d8ad51"></a>
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          <td class="memname">#define XTG_MSTERR_INTR_MINTREN_MASK&#160;&#160;&#160;0x00008000</td>
        </tr>
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<p>Master Err Interrupt Enable. </p>

</div>
</div>
<a class="anchor" id="ae797ad9c3446d0523af686f5a1360a2e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MSTRAM_INDEX_MASK&#160;&#160;&#160;0x1FFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Master RAM Index. </p>

</div>
</div>
<a class="anchor" id="adac26542aa0ea0c464a48d0c60086788"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MSTRAM_INDEX_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Master RAM Index. </p>

</div>
</div>
<a class="anchor" id="a23937f160c785883f46e3e8ac03af193"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MY_DEPEND_MASK&#160;&#160;&#160;0x1FF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>My depend command no. </p>

</div>
</div>
<a class="anchor" id="a43673c92101ad1d1af680384add5f610"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MY_DEPEND_SHIFT&#160;&#160;&#160;22</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>My depend cmd num. </p>

</div>
</div>
<a class="anchor" id="a50464785b101e677032e4956a4592a0e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_OTHER_DEPEND_MASK&#160;&#160;&#160;0x1FF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Other depend Command no. </p>

</div>
</div>
<a class="anchor" id="a18b2f14ba07703fe0e078d326496231d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_OTHER_DEPEND_SHIFT&#160;&#160;&#160;13</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Other depend cmd num. </p>

</div>
</div>
<a class="anchor" id="a1db016038b97b33a8f6ac84a1aeb9b05"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_ADDRMODE_MASK&#160;&#160;&#160;0x3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Address mode. </p>

</div>
</div>
<a class="anchor" id="a428fb28a58206c20a2bda291fd8966a4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_ADDRMODE_SHIFT&#160;&#160;&#160;24</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Address mode. </p>

</div>
</div>
<a class="anchor" id="a04045088459eca529c1dc34dccdcc889"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_ADDRRANGE_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Address Range. </p>

</div>
</div>
<a class="anchor" id="a0ecc1e7486d1e09d8e771674e163e215"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_ADDRRANGE_SHIFT&#160;&#160;&#160;20</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Address Range. </p>

</div>
</div>
<a class="anchor" id="ab433ce1c62131e78ac0d5376c85cfeab"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_COUNT_MASK&#160;&#160;&#160;0xFFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Repeat/Delay count. </p>

</div>
</div>
<a class="anchor" id="aec8150e49af318bfd447d9b3cbf80734"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_COUNT_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Repeat/Delay count. </p>

</div>
</div>
<a class="anchor" id="ad8b0023a1d6151920452773820e2e1a0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_DELAY_MASK&#160;&#160;&#160;0xFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FIXED RPT Delay count. </p>

</div>
</div>
<a class="anchor" id="afd5037cc1466de72917fbcdd8c87e784"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_DELAY_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FIXED RPT Delay count. </p>

</div>
</div>
<a class="anchor" id="ae2ffe39b97ed925d219f1abb0ce23916"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_DELAYRANGE_MASK&#160;&#160;&#160;0xFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Delay Range. </p>

</div>
</div>
<a class="anchor" id="a67d17cf7158e597c2307e21521e35812"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_DELAYRANGE_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Delay Range. </p>

</div>
</div>
<a class="anchor" id="a7358e0b257a66c3dea934297d4ce2e4c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_IDMODE_MASK&#160;&#160;&#160;0x1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Id mode. </p>

</div>
</div>
<a class="anchor" id="adf334f6bf0852006382b697cc4ab59ce"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_IDMODE_SHIFT&#160;&#160;&#160;28</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Id mode. </p>

</div>
</div>
<a class="anchor" id="a5e5c93dc4a415adb31056d163fff03db"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_INTERVALMODE_MASK&#160;&#160;&#160;0x3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interval mode. </p>

</div>
</div>
<a class="anchor" id="ac10bb6f9809e4f577bd36cb5dde0354e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_INTERVALMODE_SHIFT&#160;&#160;&#160;26</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interval mode. </p>

</div>
</div>
<a class="anchor" id="aa9eeb814676b06669a3e4fe310717efe"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_ADDRMODE_CONST&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Constant Addr mode. </p>

</div>
</div>
<a class="anchor" id="a36f53cac2eca3c077bfc7691b4bae390"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_ADDRMODE_INCR&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Increment Addr mode. </p>

</div>
</div>
<a class="anchor" id="a277fae0e2fc80d4ee117d512dd487343"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_ADDRMODE_RAND&#160;&#160;&#160;2</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Random Addr mode. </p>

</div>
</div>
<a class="anchor" id="a888fa5e45c08153523c902eacb4078a8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_DELAY&#160;&#160;&#160;2</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Delay mode. </p>

</div>
</div>
<a class="anchor" id="a64bfe0cfa6be21facf834f5d49c2a706"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_FIXEDRPT&#160;&#160;&#160;3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Fixed Repeat Delay. </p>

</div>
</div>
<a class="anchor" id="a65d8f9067f4a40826da17eca055cac9e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_MASK&#160;&#160;&#160;0x7</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Opcode. </p>

</div>
</div>
<a class="anchor" id="a71baeb60d7cd7baa527e7d87378632c0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_NOP&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>NOP mode. </p>

</div>
</div>
<a class="anchor" id="ad4415c801c23c948e6c180ad252e0d8f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_RPT&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Repeat mode. </p>

</div>
</div>
<a class="anchor" id="a120a164368673bb038500e599e1501ea"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_SHIFT&#160;&#160;&#160;29</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Opcode. </p>

</div>
</div>
<a class="anchor" id="a23774b21bbe0901e320b466de35008a2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAMOP_INTERVALMODE_CONST&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Constant Interval mode. </p>

</div>
</div>
<a class="anchor" id="a2b331214337314d34e905dd2d3b5c0a2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAMOP_INTERVALMODE_RAND&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Random Interval mode. </p>

</div>
</div>
<a class="anchor" id="ae6b714a335a4b02967a37f0ead14508a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PROT_MASK&#160;&#160;&#160;0x7</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_prot line. </p>

</div>
</div>
<a class="anchor" id="a0796a27df8444fd763ccd6c0356aa8e4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PROT_SHIFT&#160;&#160;&#160;21</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_prot line. </p>

</div>
</div>
<a class="anchor" id="a31f414339e85047271ed193829b066b6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_QOS_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_qos line. </p>

</div>
</div>
<a class="anchor" id="ae3f2ee00c71bc8f847738acf83bf1c5c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_QOS_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_qos line. </p>

</div>
</div>
<a class="anchor" id="acba37550ee94c7c7022aa5a3ad946fc3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_SIZE_MASK&#160;&#160;&#160;0x7</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_size line. </p>

</div>
</div>
<a class="anchor" id="a6523ef7f08423cbc5150e3d6e55abd99"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_SIZE_SHIFT&#160;&#160;&#160;12</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_size line. </p>

</div>
</div>
<a class="anchor" id="a4955ccf9832cc09dd5f05b54f49104dd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STATIC_CNTL_RESET_MASK&#160;&#160;&#160;0x00000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Static Disable Mask. </p>

</div>
</div>
<a class="anchor" id="a820c08467cb0fc69af91e8747bf52199"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STATIC_CNTL_STEN_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Static enable Mask. </p>

</div>
</div>
<a class="anchor" id="ae82296e2d81edb5da14c813e36b604cc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STATIC_CNTL_TD_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Transfer Done Mask. </p>

</div>
</div>
<a class="anchor" id="ac0e75db08cd3774207a38bdfe78f2ac9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STATIC_CNTL_TD_SHIFT&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Transfer Done Shift. </p>

</div>
</div>
<a class="anchor" id="a2f470f08ec693fff5af6c5109f1b3ffc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STATIC_CNTL_VER_MASK&#160;&#160;&#160;0xFF000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Version Mask. </p>

</div>
</div>
<a class="anchor" id="a128106d0d3435137e96192b0386eeec4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STATIC_CNTL_VER_SHIFT&#160;&#160;&#160;24</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Version Shift. </p>

</div>
</div>
<a class="anchor" id="a6a65cb71fdd0717246547dbbe16b6e1b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STATIC_LEN_BLEN_MASK&#160;&#160;&#160;0x000000FF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Burst length Mask. </p>

</div>
</div>
<a class="anchor" id="a490ccc5cf897e6daf0e403fdb5028cc8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CFG_PDLY_MASK&#160;&#160;&#160;0xFFFF0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Programmable Delay Mask. </p>

</div>
</div>
<a class="anchor" id="aea7d215adbbf69b18fac485e2d150bd9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CFG_PDLY_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Programmable Delay Shift. </p>

</div>
</div>
<a class="anchor" id="ae44681fc73afbcdb7ae0015719f8ac47"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CFG_RANDL_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Random Length Mask. </p>

</div>
</div>
<a class="anchor" id="ae6da854602744d63b3fe0dfdc2dc22f9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CFG_RANDLY_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Random Delay Mask. </p>

</div>
</div>
<a class="anchor" id="ae0436a212983ec018bba1d0a4352f32f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CFG_RANDLY_SHIFT&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Random Delay Shift. </p>

</div>
</div>
<a class="anchor" id="a27be0cf2c90513010b73b0b8db1163dc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CFG_TDEST_MASK&#160;&#160;&#160;0x0000FF00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TDEST PORT Mask. </p>

</div>
</div>
<a class="anchor" id="acf47f8d5a9f92da3d0d5b4fd6be627a6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CFG_TDEST_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TDEST PORT Shift. </p>

</div>
</div>
<a class="anchor" id="ad4ac7a7ef3c84748869c001e04d5dade"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CNTL_RESET_MASK&#160;&#160;&#160;0x00000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Streaming Disable Mask. </p>

</div>
</div>
<a class="anchor" id="a96e6916449a1ded46ea7882b67d2d732"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CNTL_STEN_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Streaming Enable Mask. </p>

</div>
</div>
<a class="anchor" id="a4b0674a7c9f7879bf6462860641b4d89"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CNTL_TD_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Transfer Done Mask. </p>

</div>
</div>
<a class="anchor" id="a3e492e71798bc4139c136551452503fa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CNTL_TD_SHIFT&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Transfer Done Shift. </p>

</div>
</div>
<a class="anchor" id="a33aba05b605e1929b2045d76228f04f5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CNTL_VER_MASK&#160;&#160;&#160;0xFF000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Version Mask. </p>

</div>
</div>
<a class="anchor" id="a49c88fdab76f14bbf070eebcedc16ef1"></a>
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        <tr>
          <td class="memname">#define XTG_STREAM_CNTL_VER_SHIFT&#160;&#160;&#160;24</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Version Shift. </p>

</div>
</div>
<a class="anchor" id="a556bcb7b08d4170167ee65c08c7a0ebe"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XTG_STREAM_TL_TCNT_MASK&#160;&#160;&#160;0xFFFF0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Transfer Count Mask. </p>

</div>
</div>
<a class="anchor" id="a826017ee56ef1171a4d132dc12ca8341"></a>
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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_TL_TCNT_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Transfer Count Shift. </p>

</div>
</div>
<a class="anchor" id="ae28f53acd7ef1f38265f560c17c64800"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_TL_TLEN_MASK&#160;&#160;&#160;0x0000FFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Transfer Length Mask. </p>

</div>
</div>
<a class="anchor" id="a6dda4f385ddd7962f4b7978fc1c42664"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_USER_MASK&#160;&#160;&#160;0xFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_user line. </p>

</div>
</div>
<a class="anchor" id="a280ef09f695b10f97848ce74d68f7c02"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_USER_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_user line. </p>

</div>
</div>
<a class="anchor" id="a584b02e4845e493b2854d3c865aaed19"></a>
<div class="memitem">
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        <tr>
          <td class="memname">#define XTG_VALID_CMD_MASK&#160;&#160;&#160;0x1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Valid Command. </p>

</div>
</div>
<a class="anchor" id="a4387f942768e60fd471499c63ad5e7dd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_VALID_CMD_SHIFT&#160;&#160;&#160;31</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Valid Command. </p>

</div>
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<a class="anchor" id="a04a570c3b4cc407d745237050374013c"></a>
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        <tr>
          <td class="memname">#define XTrafGen_ReadCmdRam</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(Xil_In32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga1b4f5daeb95b5827db0760c1c0dc13e5">XTG_COMMAND_RAM_OFFSET</a> + (Offset))))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_ReadCmdRam returns the value read from the Command RAM specified by <em>Offset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset of the Command RAM to be read.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns the 32-bit value of the memory location.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xtrafgen__hw_8h.html#a04a570c3b4cc407d745237050374013c" title="XTrafGen_ReadCmdRam returns the value read from the Command RAM specified by Offset. ">XTrafGen_ReadCmdRam(u32 BaseAddress, u32 Offset)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ab9c29e9e8361e7dc553c689e7cfd8ee1"></a>
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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_ReadCmdRam_Msb</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(Xil_In32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga6fd650735d7eb15cc3cd76679f8b7894">XTG_COMMAND_RAM_MSB_OFFSET</a> + (Offset))))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_ReadCmdRam_Msb returns the value read from the Command RAM specified by <em>Offset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the MSB of base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset of the Command RAM to be read.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns the 32-bit value of the memory location.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xtrafgen__hw_8h.html#ab9c29e9e8361e7dc553c689e7cfd8ee1" title="XTrafGen_ReadCmdRam_Msb returns the value read from the Command RAM specified by Offset. ">XTrafGen_ReadCmdRam_Msb(u32 BaseAddress, u32 Offset)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="a60ceec5d839e8a8f1cdda74c93c425b8"></a>
<div class="memitem">
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      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_ReadMasterRam</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(Xil_In32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga5f8872e23f0ea33fda1193c114fa9224">XTG_MASTER_RAM_OFFSET</a> + (Offset))))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_ReadMasterRam returns the value read from the Master RAM specified by <em>Offset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset of the Master RAM to be read.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns the 32-bit value of the memory location.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xtrafgen__hw_8h.html#a60ceec5d839e8a8f1cdda74c93c425b8" title="XTrafGen_ReadMasterRam returns the value read from the Master RAM specified by Offset. ">XTrafGen_ReadMasterRam(u32 BaseAddress, u32 Offset)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#gaaea625b89454268bbbe7f93e309141c4">XTrafGen_AccessMasterRam()</a>.</p>

</div>
</div>
<a class="anchor" id="a29995f5e78072a8756081fed9ccb36bd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_ReadParamRam</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(Xil_In32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga3252ba966b4231b39738858474879b33">XTG_PARAM_RAM_OFFSET</a> + (Offset))))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_ReadParamRam returns the value read from the Parameter RAM specified by <em>Offset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset of the Parameter RAM to be read.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns the 32-bit value of the memory location.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xtrafgen__hw_8h.html#a29995f5e78072a8756081fed9ccb36bd" title="XTrafGen_ReadParamRam returns the value read from the Parameter RAM specified by Offset. ">XTrafGen_ReadParamRam(u32 BaseAddress, u32 Offset)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="affb7c95abd8cad50d7efa83f94ea3344"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(Xil_In32(((BaseAddress) + (RegOffset))))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_ReadReg returns the value read from the register specified by <em>RegOffset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the offset of the register to be read.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns the 32-bit value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344" title="XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...">XTrafGen_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="a25bf6ea33be9bb74e718dc810c6760f5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_WriteCmdRam</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_Out32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga1b4f5daeb95b5827db0760c1c0dc13e5">XTG_COMMAND_RAM_OFFSET</a> + (Offset)), (Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_WriteCmdRam, writes <em>Data</em> to the Command RAM specified by <em>Offset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset of the location in Command RAM to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the Command RAM.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xtrafgen__hw_8h.html#a25bf6ea33be9bb74e718dc810c6760f5" title="XTrafGen_WriteCmdRam, writes Data to the Command RAM specified by Offset. ">XTrafGen_WriteCmdRam(u32 BaseAddress, u32 Offset, u32 Data)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="afebb93dc8864de6d9466a5fd6355c117"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_WriteCmdRam_Msb</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_Out32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga6fd650735d7eb15cc3cd76679f8b7894">XTG_COMMAND_RAM_MSB_OFFSET</a> + (Offset)), (Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_WriteCmdRam_Msb, writes <em>Data</em> to the Command RAM specified by <em>Offset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the MSB of base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset of the location in Command RAM to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the Command RAM.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xtrafgen__hw_8h.html#afebb93dc8864de6d9466a5fd6355c117" title="XTrafGen_WriteCmdRam_Msb, writes Data to the Command RAM specified by Offset. ">XTrafGen_WriteCmdRam_Msb(u32 BaseAddress, u32 Offset, u32 Data)</a> </dd></dl>

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<a class="anchor" id="a8fe8b5ce12fefb6bba6acee1b89cb2a7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_WriteMasterRam</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_Out32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga5f8872e23f0ea33fda1193c114fa9224">XTG_MASTER_RAM_OFFSET</a> + (Offset)), (Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_WriteMasterRam, writes <em>Data</em> to the Master RAM specified by <em>Offset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset of the location in Master RAM to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the Master RAM.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xtrafgen__hw_8h.html#a8fe8b5ce12fefb6bba6acee1b89cb2a7" title="XTrafGen_WriteMasterRam, writes Data to the Master RAM specified by Offset. ">XTrafGen_WriteMasterRam(u32 BaseAddress, u32 Offset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__trafgen__v3__2.html#gaaea625b89454268bbbe7f93e309141c4">XTrafGen_AccessMasterRam()</a>.</p>

</div>
</div>
<a class="anchor" id="affbc767805f25351f801dc04114d513f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_WriteParamRam</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_Out32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga3252ba966b4231b39738858474879b33">XTG_PARAM_RAM_OFFSET</a> + (Offset)), (Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_WriteParamRam, writes <em>Data</em> to the Parameter RAM specified by <em>Offset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset of the location in Parameter RAM to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the Parameter RAM.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xtrafgen__hw_8h.html#affbc767805f25351f801dc04114d513f" title="XTrafGen_WriteParamRam, writes Data to the Parameter RAM specified by Offset. ">XTrafGen_WriteParamRam(u32 BaseAddress, u32 Offset, u32 Data)</a> </dd></dl>

</div>
</div>
<a class="anchor" id="ac6e57b26c1f5674deb7c571dc319bf9e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_Out32(((BaseAddress) + (RegOffset)), (Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_WriteReg, writes <em>Data</em> to the register specified by <em>RegOffset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the offset of the register to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e" title="XTrafGen_WriteReg, writes Data to the register specified by RegOffset. ">XTrafGen_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

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